System and method to reduce noise in a substrate

ABSTRACT

Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of the following U.S. patentapplications: Ser. No. 10/294,880 filed on Nov. 14, 2002, Ser. No.10/706,218 filed on Nov. 12, 2003, Ser. No. 10/801,260 filed on Mar. 15,2004, and Ser. No. 10/801,290 filed on Mar. 15, 2004, all of which makereference to, claim priority to and claim the benefit of U.S.Provisional Patent Application Ser. No. 60/402,095 filed on Aug. 7,2002.

All of the above stated applications are incorporated herein byreference in their respective entireties.

BACKGROUND OF THE INVENTION

As more and more functional blocks are added, for example, to a chip, anintegrated circuit (IC), or an integrated system or device, the risk ofgeneration and propagation of noise between different functional blocks,or within a functional block, may become quite substantial.

An exemplary conventional complementary metal oxide semiconductor (CMOS)transistor arrangement is illustrated in FIG. 1. As shown in FIG. 1, theconventional CMOS transistor arrangement 10 includes an n-channel MOS(NMOS) transistor 30 and a p-channel MOS (PMOS) transistor 40. Theconventional CMOS arrangement 10 also includes a p-substrate 20 (e.g., ap⁻-substrate). The NMOS transistor 30 is disposed in the p-substrate 20.The NMOS transistor 30 includes a p⁺-body (B), an n⁺-source (S) and ann⁺-drain (D) disposed in the p-substrate 20. A voltage source V_(SS) 7having a ground is coupled to the p⁺-body (B) and the n⁺-source (S) ofNMOS transistor 30. An input line 5 is coupled to a gate (G) of the NMOStransistor 30. An output line 15 is coupled to the n⁺-drain (D) of theNMOS transistor 30. The PMOS transistor 40 includes an n-well 50 that isdisposed in the p-substrate 20. The PMOS transistor 40 also includes ann⁺-body (B), a p⁺-source (S) and a p⁺-drain (D) disposed in the n-well50. A voltage source V_(DD) 17 is coupled to the p⁺-source (S) and then⁺-body (B) of PMOS transistor 50. The input line 5 is also coupled to agate of the PMOS transistor 40. The output line 15 is also coupled tothe p⁺-drain (D) of the PMOS transistor 40.

During normal operation of the conventional CMOS transistor arrangement10, voltage sources V_(SS) 7 and V_(DD) 17 may be noisy. For example,noise may be caused by other circuitry found on or coupled to the chipthat may directly or indirectly affect the voltage sources V_(SS) 7 andV_(DD) 17. High swing or high power devices, such as data drivers in awire line communication system or transmitters in wirelesscommunications systems, may be sources of noise. Noise may also becaused, for example, by the driving of active circuits. In one example,the voltage sources may be coupled to active circuitry (e.g., activeportions of an inverter circuit) which may cause transient currents toflow during signal transitions from a high level to a low level or froma low level to a high level. In another example, noise may be caused bytransitions in a signal propagated or generated by the chip.

In the NMOS transistor 30, if the voltage source V_(SS) 7 is noisy, thenthe noise may propagate to the p-substrate 20 via, for example, at leastthrough the resistive coupling 9 between the p⁺-body (B) and thep-substrate 20. In the PMOS transistor 40, if the voltage source V_(DD)17 is noisy, then the noise may propagate to the n-well 50 via then⁺-body (B) of the PMOS transistor 40 via a resistive coupling 19. Thenoise in the n-well 50 may propagate to the p-substrate 20 via, forexample, at least the capacitive coupling 29 between the n-well 50 andthe p-substrate 20. If the noise is able to propagate to the p-substrate20, then noise may propagate to or otherwise affect other circuits on oroff the chip that may be coupled to the p-substrate 20.

FIG. 1A shows another conventional CMOS arrangement 10, which is similarto the conventional CMOS arrangement 10 shown in FIG. 1, except that aquieter voltage source V_(SS) 3 may be coupled to the p⁺-body (B) of theNMOS transistor 30 and a noisy voltage source V_(SS) 7 may be coupled tothe n⁺-source (S) of the NMOS transistor 30. Thus, less noise isresistively coupled from the p⁺-body (B) to the p-substrate 20. To alesser extent, noise may be capacitively coupled between the n⁺-sourceand the p-substrate 20. Noise may be coupled from the PMOS transistor 40to the p-substrate 20, as described above with respect to theconventional CMOS arrangement 10, and as shown in FIG. 1. In the CMOSarrangement of FIG. 1A, noise may substantially propagate to thep-substrate 20. Accordingly, there is a need to mitigate noise in thesubstrate of a chip.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention may be found in a system for reducingnoise in a chip. The system may comprise a substrate doped with a firstdopant and a first well doped with a second dopant. The first well maybe disposed atop the substrate. A first transistor may be disposed in asecond well and a second transistor may be disposed in a third well. Thesecond well and the third well may be disposed within the first well.

In an embodiment according to the present invention, the firsttransistor may be a PMOS transistor.

In an embodiment according to the present invention, the secondtransistor may be an NMOS transistor.

In an embodiment according to the present invention, the system mayfurther comprise a noisy voltage source coupled to a source of the firsttransistor.

In an embodiment according to the present invention, the system mayfurther comprise a quiet voltage source coupled to a body of the firsttransistor.

In an embodiment according to the present invention, a body of the firsttransistor may be resistively coupled to the second well.

In an embodiment according to the present invention, the system mayfurther comprise a noisy voltage source. A body and a source of thesecond transistor may both be coupled to the noisy voltage source.

In an embodiment according to the present invention, the body of thesecond transistor may be capacitively coupled to the substrate.

In an embodiment according to the present invention, the first well maybe a deep well.

In an embodiment according to the present invention, the second well maybe doped with the second dopant.

In an embodiment according to the present invention, the third well maybe doped with the first dopant.

Aspects of the present invention may be found in a method for reducingnoise in a chip. The method may comprise disposing a substrate layerwithin the chip, disposing a transistor layer within the chip, shieldingthe substrate layer from the transistor layer by disposing a shieldinglayer therebetween, and coupling the transistor layer to the shieldinglayer employing a first transistor type.

In an embodiment according to the present invention, the method mayfurther comprise coupling a quiet voltage source to the first transistortype and coupling a second transistor type coupled to the shieldinglayer.

In an embodiment according to the present invention, the secondtransistor type may be an n-type transistor and the first transistortype may be a p-type transistor.

In an embodiment according to the present invention, the method mayfurther comprise disposing the second transistor type within thetransistor layer and resistively coupling the second transistor type tothe shielding layer.

In an embodiment according to the present invention, the method mayfurther comprise coupling a first noisy voltage source to a source ofthe second transistor type.

In an embodiment according to the present invention, the method mayfurther comprise disposing the first transistor type within thetransistor layer.

In an embodiment according to the present invention, the method mayfurther comprise capacitively coupling the first transistor type to theshielding layer and capacitively coupling the shielding layer to thesubstrate layer.

In an embodiment according to the present invention, the shielding layermay be a deep N-well.

Certain embodiments of the present invention may be found in, forexample, a system that reduces noise in a substrate of a chip. Aspectsof the system may comprise a substrate and a first well disposed on topof the substrate. The first well may be a deep well. A second well and athird well may also both be disposed within the first well. A firsttransistor may be disposed in the second well. A quiet voltage sourcemay be connected to a body of the first transistor and a secondtransistor may be disposed in the third well. The first transistor maybe a PMOS transistor and the second transistor may be an NMOStransistor. A noisy voltage source may be coupled to a source of thefirst transistor. A body of the first transistor may be resistivelycoupled to the second well.

The system may further comprise a noisy voltage source, wherein a bodyand a source of the second transistor may both be coupled to the noisyvoltage source. The body of the second transistor may be capacitivelycoupled to the substrate. The substrate and the third well may be dopedwith a first dopant, wherein the first well and the second well may alsobe doped with a second dopant.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1 AND 1A show embodiments of conventional complementary metaloxide semiconductor (CMOS) transistor arrangements.

FIG. 2 shows an embodiment of a CMOS transistor arrangement according tothe present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows an embodiment of a complementary metal oxide semiconductor(CMOS) transistor arrangement 60 in accordance with the presentinvention. The CMOS transistor arrangement 60 may include a p-substrate70, a deep n-well 80, an n-channel MOS (NMOS) transistor 90, and ap-channel MOS (PMOS) transistor 100. The NMOS transistor 90 may include,for example, a p⁺-body (B), an n⁺-source (S), and an n⁺-drain (D), whichmay be disposed in a p-well 110. The p-well 110 may be an isolatedp-well, for example, and may be disposed between two n-wells 120 and thedeep n-well 80. A voltage source V_(SS) 170 having an electrical groundmay be coupled to the p⁺-body (B) and the n⁺-source (S) of the NMOStransistor 90. An input signal line 150 may be coupled to a gate of theNMOS transistor 90. An output signal line 160 may be coupled to then⁺-drain of the NMOS transistor 90.

The PMOS transistor 100 may include, for example, an n⁺-body (B), ap⁺-source (S), and a p⁺-drain (D), which may be disposed in an n-well120. A first voltage source V_(DD) 130 may be coupled to the p⁺-source(S). A second voltage source V_(DD) 140 may be coupled to the n⁺-body(B) of the PMOS transistor 100. In an embodiment according to thepresent invention, the second voltage source V_(DD) 140 may be lessnoisy than the first voltage source V_(DD) 130. In this regard, V_(DD)140 may be a quieter voltage source in comparison to the voltage sourceV_(DD) 130. The input signal line 150 may be coupled to a gate of thePMOS transistor 100. The output signal line 160 may be coupled to thep⁺-drain (D) of the PMOS transistor 100.

The voltage source V_(DD) 130 and the quieter voltage source V_(DD) 140may be different voltage sources. The quieter voltage source V_(DD) 140may be a dedicated voltage source that is not coupled to some sources ofnoise, for example, and may be an active component of a transistor. Thequieter voltage source V_(DD) 140 may be dedicated, for example, to aguard bar for well taps or substrate taps. Alternatively, the voltagesource V_(DD) 130 and the quieter voltage source V_(DD) 140 may becoupled to the same voltage source. However, the quieter voltage sourceV_(DD) 140 may be isolated or separated from the voltage source V_(DD)130, wherein less noise may be carried by the quieter voltage sourceV_(DD) 140.

In operation, the voltage source V_(SS) 170 and the voltage sourceV_(DD) 130 may be noisy due to a number of factors, some of which aredescribed herein. For example, noise may be caused by circuitry found onor coupled to the chip that may directly or indirectly affect thevoltage sources V_(SS) 170 and/or V_(DD) 130. High swing or high powerdevices, such as data drivers in a wire line communication system ortransmitters in wireless communications systems, may be sources ofnoise. Noise may also be caused, for example, by the driving of activecircuits. In one example, the voltage sources may be coupled to activecircuitry (e.g., active portions of an inverter circuit), which maycause transient currents to flow during signal transitions from a highlevel to a low level or from a low level to a high level. In anotherexample, noise may be caused by transitions in a signal propagated orgenerated by the chip and/or associated circuitry.

In accordance with an inventive CMOS transistor arrangement 60, onesource of noise is that the voltage sources V_(SS) 170 and/or V_(DD) 130may be coupled to the sources of the NMOS transistor 90 and the PMOStransistor 100. Thus, for example, when the circuit is in a transitionalstate, such as during a signal transition from a high level to a lowlevel or from a low level to a high level, a transient current may flowbetween the voltage sources V_(SS) 170 and/or V_(DD) 130. Notably, ifother devices (e.g., other CMOS transistor arrangements) share thevoltage sources V_(SS) 170 and/or V_(DD) 130, then the noise generatedby the transient current flows may be substantial.

The noise in the voltage source V_(SS) 170 may flow into the body (B)and the source (S) of the NMOS transistor 90. The body (B) of the NMOStransistor 90 may be resistively coupled 180 to the p-well 110 and thesource (S) of the NMOS transistor 90 may be capacitively coupled 190 tothe p-well 110. The resistive coupling 180 may be much more substantialthan the capacitive coupling 190. Accordingly, most of the noise in thep-well 110 may be associated with the p⁺-body of the NMOS transistor 90.For noise in the p-well 110 to reach the p-substrate 70, the noise mayneed to pass through two capacitive couplings: a capacitive coupling 200between the p-well 110 and the deep n-well 80, and a capacitive coupling210 between the deep n-well 80 and the p-substrate 70. Importantly, thecapacitive coupling may generally be fairly weak, but the capacitivecoupling may be even weaker when the couplings are placed in series.Thus, in an embodiment of the present invention, the resistive couplings180, 200, and 210 between the p⁺-body (B) of the NMOS transistor 90through to the p-substrate 70 may be replaced with a much weakercapacitive coupling.

The noise in voltage source V_(DD) 130 may flow into the p⁺-source (S)of the PMOS transistor 100. In this embodiment, the present inventionmay employ a quieter voltage source V_(DD) 140, which may be coupled tothe n⁺-body (B) of the PMOS transistor 100. The p⁺-source (S) of thePMOS transistor 100 may be capacitively coupled 220 to the n-well 120and the n⁺-body (B) of the PMOS transistor 100 may be resistivelycoupled 230 to the n-well 120. Because the resistive coupling 230 may bemore substantial than the capacitive coupling, the noise in the n-well120 may be mostly from the quieter voltage source V_(DD) 140.Advantageously, noise in the n-well 120 may be substantially reduced, byconnecting the quieter voltage source V_(DD) 140 to the n⁺-body (B) ofthe PMOS transistor 100. The n-well 120 and the deep n-well 80 may beresistively coupled 240. Notably, the deep n-well 80 may provide asubstantial amount of resistance to noise, thereby further reducing anynoise propagating through PMOS resistor 100 and reaching substrate 70.The deep n-well 80 and the p-substrate 70 may be capacitively coupled,which may offer the noise only a weak coupling.

Although illustrated in use with a CMOS transistor arrangement, thepresent invention need not be so limited. The present invention may alsobe applicable for use with other types of transistors and/or other typesof transistor arrangements. Notably, in an embodiment of the presentinvention, quiet voltage source V_(DD) may be used to replace aconventional voltage source V_(SS) without an area penalty. In thisregard, the area used by voltage source V_(DD) may replace the area usedby voltage source V_(SS), for example, in a block or standardresistor/transistor logic (RTL) arrangement. The present invention mayalso be applicable for use with other electrical, magnetic orelectromagnetic components and/or circuits. Furthermore, although one ormore of the embodiments described above may employ semiconductormaterials (e.g., semiconductor material, compound semiconductormaterial, etc.), the present invention may also employ other materials(e.g., ceramics, metals, alloys, superconductors, etc.) and/orcombinations thereof. In addition, the present invention may alsocontemplate employing different dopant types, dopant schemes, and/ordopant concentrations other than and/or in addition to theabove-described dopant types, dopant schemes, and/or dopantconcentrations.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A method for reducing noise in an electronic device, the methodcomprising: shielding a substrate layer from a circuit layer employing ashielding layer; coupling a first circuit to the shielding layer,coupling a second circuit to the shielding layer; and coupling theshielding layer to the substrate layer, wherein coupling the shieldinglayer to the substrate layer reduces noise transfer in the electronicdevice.
 2. The method according to claim 1, wherein shielding thesubstrate layer from the circuit layer comprises disposing the shieldinglayer between the substrate layer and the circuit layer.
 3. The methodaccording to claim 1, wherein shielding the substrate layer from thecircuit layer comprises disposing a deep N-well between the substratelayer and the circuit layer.
 4. The method according to claim 1, furthercomprising coupling one of a quiet voltage source and a noisy voltagesource to the first circuit.
 5. The method according to claim 1, furthercomprising coupling one of a quiet voltage source and a noisy voltagesource to the second circuit.
 6. The method according to claim 1,wherein coupling the first circuit to the shielding layer comprisescapacitively coupling the first circuit to the shielding layer.
 7. Themethod according to claim 1, wherein coupling the second circuit to theshielding layer comprises resistively coupling the second circuit to theshielding layer.
 8. The method according to claim 1, further comprising:coupling a noisy voltage source to the second circuit; and coupling aquiet voltage source to the first circuit.
 9. The method according toclaim 8, further comprising producing approximately equal voltage levelsfrom the noisy voltage source and the quiet voltage source.
 10. Themethod according to claim 1, further comprising: coupling a quietvoltage source to the second circuit; and coupling a noisy voltagesource to the first circuit.
 11. The method according to claim 10,further comprising producing approximately equal voltage levels from thenoisy voltage source and the quiet voltage source.
 12. The methodaccording to claim 1, wherein the first circuit comprises a firsttransistor.
 13. The method according to claim 12, wherein the firsttransistor comprises a p-type transistor.
 14. The method according toclaim 13, further comprising coupling a voltage source to a source ofthe p-type transistor, wherein the p-type transistor comprises anp-channel metal oxide semiconductor (PMOS) transistor.
 15. The methodaccording to claim 13, further comprising coupling a voltage source to abody of the p-type transistor, wherein the p-type transistor comprisesan p-channel metal oxide semiconductor (PMOS) transistor.
 16. The methodaccording to claim 1, wherein the second circuit comprises a secondtransistor.
 17. The method according to claim 16, wherein the secondtransistor comprises an n-type transistor.
 18. The method according toclaim 17, further comprising coupling a voltage source to a source ofthe n-type transistor, wherein the n-type transistor comprises ann-channel metal oxide semiconductor (NMOS) transistor.
 19. The methodaccording to claim 17, further comprising coupling a voltage source to abody of the n-type transistor, wherein the n-type transistor comprisesan n-channel metal oxide semiconductor (NMOS) transistor.
 20. The methodaccording to claim 1, wherein coupling the shielding layer to thesubstrate layer comprises capacitively coupling the shielding layer tothe substrate layer.